Static Timing Analysis Engineer, Full-Chip STA

Static Timing Analysis Engineer, Full-Chip STA corporate_fare Google place Mountain View, CA, USA bar_chart Mid Mid Experience driving progress, solving problems, and mentoring more junior team members; deeper expertise and applied knowledge within relevant area. Google | Mountain View, CA, USA Minimum qualifications Bachelor's degree in Electrical Engineering or Computer Science, or equivalent practical experience. 4 years of technical experience in silicon timing closure and chip integration. Experience in one or more static timing tools (e.g., PrimeTime, Tempus). Experience with Static Timing Analysis (STA) signoff constraint authoring for full-chip level, tapeout signoff requirements, checklists, and associated automation. Experience delivering silicon. Learn more share Share Static Timing Analysis Engineer, Full-Chip STA link Copy link email Email a friend