About Marvell

Marvell’s semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, and carrier architectures, our innovative technology is enabling new possibilities.

At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead.

Your Team, Your Impact

The AI era has fundamentally changed what a semiconductor package is. A package is no longer a container for a chip — it is the architecture. As AI accelerators push beyond the reticle limit of any single die, the package has become the integration layer where compute silicon, high-bandwidth memory, optical I/O, and die-to-die interconnects are assembled into a unified system. At Marvell, the advanced packaging team is where that integration happens — for the custom XPUs, AI accelerators, and high-speed connectivity platforms that the world's largest hyperscalers depend on to scale their AI infrastructure.

Marvell's packaging work is production-qualified and shipping at hyperscale. The team developed an industry-first modular RDL interposer platform that enables multi-die AI accelerator designs 2.8x larger than the largest possible single-chip implementation — integrating over 1,390mm² of silicon alongside HBM3/3E memory stacks across six redistribution layers, with shorter die-to-die interconnects and supply chain flexibility that traditional silicon interposers cannot match. The same team is integrating Co-Packaged Optics directly into custom XPU packages, enabling XPU-to-XPU connections at distances 100x longer than electrical cabling with higher bandwidth density and lower power. These are not research prototypes. They are production platforms, qualified with major hyperscalers and ramping now.

The problems this team works on — signal integrity at 224G+ SerDes speeds across multi-die substrates, power delivery for XPU packages approaching 1,000W, thermal management for chiplet stacks with HBM, mechanical reliability across advanced 2.5D and 3D integration schemes — are among the most technically demanding in the semiconductor industry. They are also among the most directly connected to doctoral research in electrical engineering, materials science, and applied physics. Marvell's Ph.D. Intern Program places doctoral candidates inside these active packaging development efforts, working on problems that are inseparable from the research they are already pursuing. What you will take away is something no university lab can replicate: the experience of solving a packaging problem that ships inside the world's most advanced AI silicon.

What You Can Expect

As our Ph.D. Advanced Packaging & Physical Integration Intern, every day you will work on packaging design and analysis challenges tied directly to production AI accelerator and connectivity platforms. Specifically, you can expect to:

• Perform signal integrity (SI) and power integrity (PI) analysis for high-speed interfaces — including 224G SerDes, die-to-die interconnects, and HBM interfaces — across multi-die package substrates and interposers

• Develop and execute thermal and mechanical simulation models for advanced 2.5D and 3D chiplet packages, evaluating heat dissipation, warpage, and reliability under production conditions

• Contribute to physical design and layout of package substrates, RDL interposers, and chiplet integration schemes for custom AI accelerator platforms

• Collaborate with chip design, assembly, and test engineering teams to validate packaging assumptions against silicon measurements and production data

• Use industry-standard EDA and simulation tools — including Ansys, Cadence Sigrity, or equivalent — to model and optimize package-level electrical, thermal, and mechanical performance

• Present analysis results and design recommendations to the engineering team and contribute to packaging design reviews

What We're Looking For

To thrive in this role, you must have hands-on research experience in semiconductor packaging, signal integrity, or a closely related physical design discipline. Specifically:

• Currently enrolled in a Ph.D. program in Electrical Engineering, Materials Science, Mechanical Engineering, or a related field, with a research focus in advanced packaging, signal/power integrity, thermal engineering, or heterogeneous integration

• Demonstrate research or project experience in one or more of the following: package-level SI/PI analysis, thermal-mechanical simulation, 2.5D/3D chiplet integration, substrate or interposer design, or high-speed interconnect characterization

• Apply strong fundamentals in electromagnetics, heat transfer, or materials mechanics — sufficient to build and interpret simulation models that inform real packaging design decisions

• Use simulation tools relevant to your research area (Ansys HFSS, Ansys Icepak, Cadence Sigrity, or equivalent) with confidence and independence

• Communicate analysis results and design tradeoffs clearly — you will present your work to the engineering team and defend your recommendations

Preferred Qualifications

• Experience with high-speed serial interface SI analysis — including eye diagram analysis, impedance matching, crosstalk, and return loss — at 100G/lane speeds or above

• Familiarity with advanced packaging technologies including CoWoS, FOPLP, RDL interposers, or flip-chip BGA

• Exposure to co-packaged optics (CPO) integration, optical engine assembly, or photonic-electronic co-design

• Experience with power delivery network (PDN) design and analysis for high-current, high-frequency applications

• Familiarity with design-for-manufacturing (DFM) and reliability considerations for chiplet-based multi-die packages

Expected Base Pay Range (USD)

37 - 73, $ per hour.

The successful candidate’s starting base pay will be determined based on job-related skills, experience, qualifications, work location and market conditions. The expected base pay range for this role may be modified based on market conditions.





Additional Compensation and Benefit Elements

Marvell is committed to providing exceptional, comprehensive benefits that support our employees at every stage - from internship to retirement and through life’s most important moments. Our offerings are built around four key pillars: financial well-being, family support, mental and physical health, and recognition. Highlights for our interns: medical, dental, and vision coverage, perks and discounts, robust mental health resources to prioritize emotional well-being, and paid holidays. Additional compensation may be available for intern PhD candidates. We look forward to sharing more with you during the interview process.

All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability or protected veteran status.

Any applicant who requires a reasonable accommodation during the selection process should contact Marvell HR Helpdesk at TAOps@marvell.com.

Interview Integrity

To support fair and authentic hiring practices, candidates are not permitted to use AI tools (such as transcription apps, real-time answer generators like ChatGPT or Copilot, or automated note-taking bots) during interviews.

These tools must not be used to record, assist with, or enhance responses in any way. Our interviews are designed to evaluate your individual experience, thought process, and communication skills in real time. Use of AI tools without prior instruction from the interviewer will result in disqualification from the hiring process.

This position may require access to technology and/or software subject to U.S. export control laws and regulations, including the Export Administration Regulations (EAR). As such, applicants must be eligible to access export-controlled information as defined under applicable law. Marvell may be required to obtain export licensing approval from the U.S. Department of Commerce and/or the U.S. Department of State. Except for U.S. citizens, lawful permanent residents, or protected individuals as defined by 8 U.S.C. 1324b(a)(3), all applicants may be subject to an export license review process prior to employment.

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