Company:

Qualcomm Technologies, Inc.

Job Area:

Engineering Group, Engineering Group > Analog Mixed Signal Design

General Summary:

QCT mixed-signal IP design team is looking for talented analog integrated circuit designers at various levels to help with designing high-speed, high-performance and low-power mixed-signal IPs (SerDes, DDR, PLL, DAC, ADC, sensors, etc.) for Qualcomm’s products targeted for 5G, AI/ML, compute, and automotive applications. QCT mixed-signal design team consists of architects and ASIC designers, protocol experts, signal processing engineers, and algorithm designers and we are looking for new talents in the area of analog circuit design for our ASICs.

Responsibilities:

1. Work in our analog design team for schematic capture and simulations and participate in architecture definition and analog/digital design partitioning.

2. Schematic capture and simulations in the Cadence Virtuoso tool suite.

3. Work with cross functional teams (i.e. layout and digital teams)

4. Work with testing team for silicon bringup and debugging

Required for this Role

• Master's degree in Electrical Engineering or related field.
• Demonstrated interest in analog circuit design by course selections and/or work experience. 
• Experience working with ASIC design tools such as Cadence Virtuoso.

Preferred Qualifications

• Several years of industry experience in the area of analog integrated circuit/system design. 
• Experience as an high speed analog designer of mixed-signal IPs, such as CTLE, CDR, PLL RXAFE, PLL, DAC, ADC
• Familiar with Matlab and Python and good understanding of architecture, system and integration aspects for mixed-signal
• Good understanding of design for yield and production challenges with high speed serial links
• Good understanding of Signals and Systems, Sampled Domain signal processing a plus

Minimum Qualifications:

• Bachelor's Degree in Electrical Engineering with 2+ years of experience with analog or mixed-signal integrated circuit design in nanometer planar CMOS or FinFET and 4+ years of ASIC design, verification, or related work experience.
OR
Master's degree in Electrical Engineering or related field and 4+ years of ASIC design, verification, or related work experience.
OR
PhD in Electrical Engineering or related field and 2+ of years ASIC design, verification, or related work experience.

• 2+ years of experience using one or more design tools (e.g., CADENCE, SPICE, MATLAB, and/or Verilog/VHDL).

Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries).

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Pay range

and Other Compensation & Benefits:

$145,600.00 - $218,400.00

The above pay scale reflects the broad, minimum to maximum, pay scale for this job code for the location for which it has been posted. Even more importantly, please note that salary is only one component of total compensation at Qualcomm.  We also offer a competitive annual discretionary bonus program and opportunity for annual RSU grants (employees on sales-incentive plans are not eligible for our annual bonus).  In addition, our highly competitive benefits package is designed to support your success at work, at home, and at play. Your recruiter will be happy to discuss all that Qualcomm has to offer – and you can review more details about our US benefits at this link.

If you would like more information about this role, please contact Qualcomm Careers.