AIML enhanced Design/Verification Methodology Engineer

This role has been designed as ‘’Onsite’ with an expectation that you will primarily work from an HPE office.

Who We Are:

Hewlett Packard Enterprise is the global edge-to-cloud company advancing the way people live and work. We help companies connect, protect, analyze, and act on their data and applications wherever they live, from edge to cloud, so they can turn insights into outcomes at the speed required to thrive in today’s complex world. Our culture thrives on finding new and better ways to accelerate what’s next. We know varied backgrounds are valued and succeed here. We have the flexibility to manage our work and personal needs. We make bold moves, together, and are a force for good. If you are looking to stretch and grow your career our culture will embrace you. Open up opportunities with HPE.

Job Description:

We are seeking a Design/Verification Engineer with exposure to AIML methodologies to join our team. In this role, you will be responsible for developing and executing comprehensive verification strategies for complex digital designs using AIML enhanced methodologies. You will architect, build, and maintain UVM-based testbench environments, drive coverage-driven verification closure, and collaborate closely with design and system engineering teams to ensure silicon quality from RTL to tapeout. This is a high-impact position for someone who thrives on solving intricate design/verification challenges using AIML methodologies.

Key Responsibilities

• Use both “classical” and Generative-AI methodologies to architect, develop, and maintain agents, skills, and other AI based infra-structures. The ideal person will have balanced knowledge of chip design and AIML methodologies to contribute meaningfully to the creation of architecture, design, verification, and physical design assets. These includes but not limited to:   

• Creating UVM-based testbench environments from ground up or enhance the existing ones. Creating verification plans with clear coverage goals and closure criteria. Performing root cause analysis of failures and work with design teams to drive resolution. 

• Automating generation of RTL from spec.  

• Evaluation of industry tools.  

Minimum Qualifications

• Bachelor's degree in Electrical Engineering, Computer Engineering, or Computer Science (or equivalent). 

• 1 - 5 years of hands-on Design/Verification experience in an ASIC or SoC environment. 

• Deep familiarity with AIML concepts and workflows — including awareness of agentic workflows, APIs, model selection, etc. 

• Strong proficiency in SystemVerilog for verification (classes, constraints, functional coverage, assertions/SVA). 

• Solid understanding of digital design fundamentals (RTL, timing, synthesis constraints). 

• Experience with industry-standard simulation tools (e.g., Synopsys VCS, Cadence Xcelium, Mentor Questa). 

• Proven ability to develop and drive verification plans to closure. 

• Effective communication and collaboration skills in cross-functional team settings. 

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Preferred Qualifications

• Master's or Ph.D. in Electrical Engineering or Computer Science. 

• Academic or professional class projects or coursework in networking, communication protocols (e.g., Ethernet, PCIe, USB, AMBA/AXI, SPI, I2C, UART), or related areas. 

• Experience verifying high-speed serial interfaces or protocol-level IP blocks. 

• Familiarity with formal verification tools and techniques (e.g., JasperGold, VC Formal). 

• Experience with emulation and FPGA prototyping platforms (e.g., Palladium, Protium, Veloce). 

• Knowledge of scripting languages (Python, Perl, TCL) for automation of verification workflows and regression infrastructure. 

• Experience with power-aware verification (UPF/CPF) or mixed-signal verification. 

• Contributions to verification methodology development or published work in the field. 

What We Can Offer You:

Health & Wellbeing

We strive to provide our team members and their loved ones with a comprehensive suite of benefits that supports their physical, financial and emotional wellbeing.

Personal & Professional Development

We also invest in your career because the better you are, the better we all are. We have specific programs catered to helping you reach any career goals you have — whether you want to become a knowledge expert in your field or apply your skills to another division.

Unconditional Inclusion

We are unconditionally inclusive in the way we work and celebrate individual uniqueness. We know varied backgrounds are valued and succeed here. We have the flexibility to manage our work and personal needs. We make bold moves, together, and are a force for good.

Let's Stay Connected:

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Job:

Engineering

Job Level:

TCP_01

"The expected salary/wage range for this position is provided below. Actual offer may vary from this range based upon geographic location, work experience, education/training, and/or skill level.
– United States of America: Annual Salary USD 81,400 - 164,400 in California
The listed salary range reflects base salary. Variable incentives may also be offered."

Information about employee benefits offered in the US can be found at https://myhperewards.com/main/new-hire-enrollment.html

HPE is an Equal Employment Opportunity/ Veterans/Disabled/LGBT employer. We do not discriminate on the basis of race, gender, or any other protected category, and all decisions we make are made on the basis of qualifications, merit, and business need. Our goal is to be one global team that is representative of our customers, in an inclusive environment where we can continue to innovate and grow together. Please click here: Equal Employment Opportunity.

Hewlett Packard Enterprise is EEO Protected Veteran/ Individual with Disabilities.

HPE will comply with all applicable laws related to employer use of arrest and conviction records, including laws requiring employers to consider for employment qualified applicants with criminal histories.

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