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We are now looking for a motivated Senior Timing Closure Engineer to join our dynamic and growing Circuit Solutions Group! If you are a highly motivated individual who excels at improving netlist and timing quality and enjoys solving complex technical challenges through collaboration, we want to hear from you.

What you'll be doing:

• Participate in groundbreaking processor design in deep submicron technologies.

• Work as part of a global circuits team alongside custom circuit designers to drive timing analysis and closure of custom circuit macros (digital, semi-custom and mixed-signal analog).

• Apply knowledge and experience to standardize and improve timing convergence flows working with methodology teams.

• Develop timing models and methodology for innovative and unique custom macro designs at transistor level.

• Develop timing models and methodology for standard cell and mixed-signal custom macro designs.

• Validate timing of custom circuit designs using NanoTime and various SPICE simulations to ensure proper timing of innovative circuit topologies.

• Work with circuit designers, tool developers, and methodology teams to validate transistor level timing accuracy and correctness.

• Work with PD, DFX, Clocks, and other teams on timing closure strategy, timing constraints, timing and power convergence, DFT, as well as ECO implementation.

What we need to see:

• BS (or equivalent experience) in Electrical or Computer Engineering

• 6+ years of experience for Masters and 8+ years for Bachelors with majority of experience in custom circuit timing analysis/closure.

• Expertise and in depth knowledge of industry standard transistor level STA tools such as NanoTime and timing convergence tools.

• Solid experience in timing constraints generation & management, and timing analysis/closure with mixed-signal designs.

• Basic level understanding of transistor-level circuits and SPICE simulations for correlation to static timing and noise results.

• Expertise in analysis and fixing of timing paths through ECOs including crosstalk and noise analysis.

• Knowledge in process variation effect modeling and experience in design convergence taking into account process variations.

• Familiarity with clocking specs such as jitter, IR drop, crosstalk, etc.

• Solid understanding of timing models and the usage of .libs in NanoTime as well as PrimeTime

• Great teammate with outstanding interpersonal skills.

Ways to stand out from the crowd:

• Understanding of DFT logic and experience with DFT timing closure for various modes e.g., scan, BIST, etc.

• Understanding of timing closure of digital logic/macros in AMS designs/IPs.

• Experience in critical path planning and crafting.

• Experience in methodology and/or flow development as well as automation.

• Knowledge of deep sub-micron process nodes and hands-on experience in modeling and converging timing in these nodes with strong scripting skills for flow automation; experience with TCL, Python is a plus.

Widely considered to be one of the technology world’s most desirable employers, NVIDIA offers highly competitive salaries and a comprehensive benefits package. As you plan your future, see what we can offer to you and your family www.nvidiabenefits.com/

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Your base salary will be determined based on your location, experience, and the pay of employees in similar positions. The base salary range is 168,000 USD - 264,500 USD.

You will also be eligible for equity and benefits.

Applications for this job will be accepted at least until June 15, 2026.

This posting is for an existing vacancy.

NVIDIA uses AI tools in its recruiting processes.

NVIDIA is committed to fostering an inclusive work environment and proud to be an equal opportunity employer. As we highly value diversity in our current and future employees, we do not discriminate (including in our hiring and promotion practices) on the basis of race, religion, color, national origin, gender, gender expression, sexual orientation, age, marital status, veteran status, disability status or any other characteristic protected by law.