About Marvell

Marvell’s semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, and carrier architectures, our innovative technology is enabling new possibilities.

At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead.

Your Team, Your Impact

Marvell Central Engineering (CE) develops Marvell's most advanced High-Speed SerDes (HSS) IPs covering multiple applications, Switch, Storage, Optics, etc. Acting as the engine to the company, Central Engineering provides the source of power to every business unit in Marvell system. Central System Engineering (CSE) in Central Engineering, independent of other CE functions including DSP algorithm development, circuit design, physical design, packaging, etc., is a function team responsible of validating all Marvell HSS IPs in the lab environment and supporting all Marvell business units for fast and smooth SoC production. Central Engineering AMS-IP team provides leading-edge SerDes PHY solutions and other Analog Mixed-Signal IPs to support all Marvell products.

This is a rare foundational technical management opportunity as part of our strategic expansion into Southern California. You will help shape the technical DNA and culture of Marvell's San Diego design organization.

What You Can Expect

• Hire and lead a team of layout designers.

• Assess schedules, floor plans, and risks for digital macros.

• Perform hands-on work at the macro level layout.

• Manage and track layout schedules; hire additional designers as needed.

• Assess risks and plan workarounds to meet or exceed layout schedules.

• Identify and prioritize project tasks and risks.

• Work with CAD, tech, and circuit design teams to synchronize layout schedules with overall project plans.

• Understand complex layout design concepts and communicate issues cross-functionally.

What We're Looking For

• Minimum 10+ years in analog layout design and 3+ years in management.

• Deep understanding of layout methodology from initial chip planning to tape-out.

• Experience with advanced process technology and FinFET is preferable.

• High proficiency in LVS, DRC debugging, and interpreting CALIBRE DRC, ERC, LVS reports.

• Proficient in Synopsys or CADENCE layout entry tools; programming skills in Skill, Ample, or Perl are a plus.

• Strong technical and analytical background with excellent problem-solving skills.

• Excellent verbal and written communication skills; experience in conflict resolution and consensus building.

• Proven ability to build and develop a world-class analog layout team; proactive, self-starter with strong organizational skills.

Expected Base Pay Range (USD)

138,200 - 204,460, $ per annum

The successful candidate’s starting base pay will be determined based on job-related skills, experience, qualifications, work location and market conditions. The expected base pay range for this role may be modified based on market conditions.

Additional Compensation and Benefit Elements

Marvell is committed to providing exceptional, comprehensive benefits that support our employees at every stage - from internship to retirement and through life’s most important moments. Our offerings are built around four key pillars: financial well-being, family support, mental and physical health, and recognition. Highlights include an employee stock purchase plan with a 2-year look back, family support programs to help balance work and home life, robust mental health resources to prioritize emotional well-being, and a recognition and service awards to celebrate contributions and milestones. We look forward to sharing more with you during the interview process.

All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability or protected veteran status.

Any applicant who requires a reasonable accommodation during the selection process should contact Marvell HR Helpdesk at TAOps@marvell.com.

Interview Integrity

To support fair and authentic hiring practices, candidates are not permitted to use AI tools (such as transcription apps, real-time answer generators like ChatGPT or Copilot, or automated note-taking bots) during interviews.

These tools must not be used to record, assist with, or enhance responses in any way. Our interviews are designed to evaluate your individual experience, thought process, and communication skills in real time. Use of AI tools without prior instruction from the interviewer will result in disqualification from the hiring process.

This position may require access to technology and/or software subject to U.S. export control laws and regulations, including the Export Administration Regulations (EAR). As such, applicants must be eligible to access export-controlled information as defined under applicable law. Marvell may be required to obtain export licensing approval from the U.S. Department of Commerce and/or the U.S. Department of State. Except for U.S. citizens, lawful permanent residents, or protected individuals as defined by 8 U.S.C. 1324b(a)(3), all applicants may be subject to an export license review process prior to employment.

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