Annapurna Labs is the team behind AWS Graviton- the industry's most advanced ARM-based server SoC.
We operate like a start-up with the scale of the world's largest cloud provider.

We're looking for exceptional engineers to join our Signal/Power-Integrity and Packaging team. A team that sits where the Silicon meets the Board, bridging the gap between what happens internally at the DIE and the overall system interconnect and the external memories and peer devices.
What sets us apart:
• Small team, yet a one stop shop for IP electrical integration at the DIE level, Package design, SI/PI simulations, Layout, Board-design and advanced lab characterization.
• Combining Signal-Integrity and Layout, to come up with optimized Package and PCB designs.
• Holistic view of the entire interconnect, from the DIE’s metals, through the Package, to the PCB traces, and all the way to the peer device.
• In-depth post-silicon characterization, using advanced measurement techniques, far exceeding traditional compliance measurements.
• Deep dive mentality, in both theory and the bolts and nuts that make the internal circuitry of the electrical interfaces.

The SIP (Signal-Integrity & Packaging) team is part of Annapurna-Lab’s Chip development team.
The team is dealing with the external electrical interfaces of the device, from their Signal/Power-integrity and electrical usage perspectives.
The team’s work includes close work with the BackEnd team on integrating these interfaces to the Die, the package layout design of the BGA’s substrate, Signal and power integrity simulations, and working with the system team to come up with optimal pin-out and optimal PCB breakout schemes.

As a SIP team member, you will assume responsibility for all electrical aspects of physical interfaces of advanced I/Os, PLL, Memory and SerDes interfaces, from integration at the Die level, through SI/PI simulation and package layout, to reference board design aspects.

This position is for an experienced engineer with strong background in high-speed electrical interfaces, such as DRAM, PCIe, Ethernet SerDeses. The line of work is multi-disciplinary, combining Package-Design, Back-End integration of electrical IPs, SI/PI extractions & simulations.

Key job responsibilities

• Deep dive into electrical IPs, integrated into the DIE;
• I/O ring design and close work with Backend team on floor-planning all I/O interfaces at the DIE level.
• Lead test studies of Die bump-out arrangements and Package substrate breakout.
• Lead layout test studies of package pin-out arrangements and PCB board breakout.
• Design large and complex package substrates.
• Carry advanced SI/PI extractions and simulations to validate the design from the silicon to the peer device at the board level.

Basic qualifications

• BSc or MSc in Electrical Engineering or in related field
• At least 8 years of experience in a similar role
• Experience in Layout (PCB or Package), or BackEnd integration of electrical IPs
• Familiarity with Signal and Power integrity simulation tools

Preferred qualifications

• Knowledge of Chip, Package and PCB co-design methodology.
• Knowledge in high-speed digital interfaces such as DRAM/PCIe/SerDes.
• Knowledge in power-integrity and power-delivery of low-voltage high-current
• Hands on experience with lab testing and characterization
• Familiarity with simulation/extraction tools (e.g. HFSS, Sigrity, HSpice)

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