Physical Design Engineer, FullChip/ASIC Implementation

Physical Design Engineer, FullChip/ASIC Implementation corporate_fare Google place Mountain View, CA, USA bar_chart Mid Mid Experience driving progress, solving problems, and mentoring more junior team members; deeper expertise and applied knowledge within relevant area. Google | Mountain View, CA, USA Minimum qualifications Bachelor's degree in Electrical Engineering or equivalent practical experience. 4 years of experience in physical design. Experience in one or more synthesis/PnR tools (e.g., Genus, Innovus, DC, ICC). Experience in high-performance synthesis, PnR, sign-off convergence, including STA and sign-off optimizations. Learn more share Share Physical Design Engineer, FullChip/ASIC Implementation link Copy link email Email a friend