Senior TPU Design Engineer, Silicon

Senior TPU Design Engineer, Silicon corporate_fare Google place Mountain View, CA, USA ; San Diego, CA, USA bar_chart Mid Mid Experience driving progress, solving problems, and mentoring more junior team members; deeper expertise and applied knowledge within relevant area. Google | Mountain View, CA, USA ; San Diego, CA, USA Minimum qualifications Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience. 8 years of experience with RTL design using Verilog/System Verilog and microarchitecture. 4 years of experience in leading IP/SoC design teams. Experience with ARM-based SoCs, interconnects, and ASIC methodology. Learn more share Share Senior TPU Design Engineer, Silicon link Copy link email Email a friend