TPU PCIe Design Lead

TPU PCIe Design Lead corporate_fare Google place Sunnyvale, CA, USA bar_chart Advanced Advanced Experience owning outcomes and decision making, solving ambiguous problems and influencing stakeholders; deep expertise in domain. Google | Sunnyvale, CA, USA Minimum qualifications Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience. 10 years of experience in ASIC design, including one project focused on PCIe logic. Experience debugging RTL using Verdi/VCS and automating tasks via Python or Perl. Experience in SystemVerilog/Verilog for RTL development and microarchitecture definition. Experience with PCIe protocol layers (e.g., Transaction, Data Link, and Physical) or LTSSM. Experience with Clock Domain Crossing (CDC), timing closure, or synthesis flows. Learn more share Share TPU PCIe Design Lead link Copy link email Email a friend