RTL Design Engineer, TPU and ML

RTL Design Engineer, TPU and ML corporate_fare Google place Sunnyvale, CA, USA bar_chart Mid Mid Experience driving progress, solving problems, and mentoring more junior team members; deeper expertise and applied knowledge within relevant area. Google | Sunnyvale, CA, USA Minimum qualifications Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience. 4 years of experience in ASIC RTL design, with a focus on clocking, reset, or timing-critical RTL development. Design experience optimizing for performance, power, and area. Experience with digital design fundamentals and microarchitecture design. Experience working cross-functionally with DV and PD teams. Learn more share Share RTL Design Engineer, TPU and ML link Copy link email Email a friend