Senior RTL Design Engineer, TPU

Senior RTL Design Engineer, TPU corporate_fare Google place Sunnyvale, CA, USA bar_chart Mid Mid Experience driving progress, solving problems, and mentoring more junior team members; deeper expertise and applied knowledge within relevant area. Google | Sunnyvale, CA, USA Minimum qualifications Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience. 8 years of experience in ASIC design. Experience with SystemVerilog/RTL coding. Experience with scripting languages (e.g., Tcl, Python or Perl). Learn more share Share Senior RTL Design Engineer, TPU link Copy link email Email a friend