Senior ASIC DFT Engineer, Silicon

Senior ASIC DFT Engineer, Silicon corporate_fare Google place Mountain View, CA, USA bar_chart Mid Mid Experience driving progress, solving problems, and mentoring more junior team members; deeper expertise and applied knowledge within relevant area. Google | Mountain View, CA, USA Minimum qualifications Bachelor's degree in Electrical Engineering or a related field, or equivalent practical experience. 8 years of experience with Design for Test (DFT). Experience with DFT EDA Tools (e.g., Tessent, Genus, Fusion Compiler (FC), Simvision, etc). Experience with one more more of the following: Scan insertion, Automatic Test Pattern Generation (ATPG), Gate Level Simulations and Silicon Debug, Low Power designs, Built-In Self-Test (BIST), Joint Test Action Group (JTAG), and Internal Joint Test Action Group (IJTAG) tools and flow. Learn more share Share Senior ASIC DFT Engineer, Silicon link Copy link email Email a friend