Physical Design Engineer, SoC Static Timing Analysis

Physical Design Engineer, SoC Static Timing Analysis corporate_fare Google place Tel Aviv, Israel ; Haifa, Israel bar_chart Mid Mid Experience driving progress, solving problems, and mentoring more junior team members; deeper expertise and applied knowledge within relevant area. Google | Tel Aviv, Israel ; Haifa, Israel Minimum qualifications Bachelor's degree in Electrical Engineering, a related technical field, or equivalent practical experience. 8 years of Physical Design experience including 5 years of experience with Static Timing Analysis (STA), including sign-off corner definitions, process margining, interface timing constraints, timing convergence, and setting frequency goals with technology scaling. Experience in constraints development for subsystems or full System-on-Chip (SoC) architectures. Learn more share Share Physical Design Engineer, SoC Static Timing Analysis link Copy link email Email a friend