Senior CPU RTL Design Engineer

Senior CPU RTL Design Engineer corporate_fare Google place Mountain View, CA, USA bar_chart Mid Mid Experience driving progress, solving problems, and mentoring more junior team members; deeper expertise and applied knowledge within relevant area. Google | Mountain View, CA, USA Minimum qualifications Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience. 8 years of experience in implementation of CPU cache subsystems, including load-store unit or private/shared L2/L3 designs. Experience with RTL language (e.g. System Verilog) and related design processes (e.g., Lint, UPF). Learn more share Share Senior CPU RTL Design Engineer link Copy link email Email a friend