Physical Design Lead, Static Timing Analysis corporate_fare Google place Sunnyvale, CA, USA bar_chart Advanced Advanced Experience owning outcomes and decision making, solving ambiguous problems and influencing stakeholders; deep expertise in domain. Google | Sunnyvale, CA, USA Minimum qualifications Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience. 10 years of experience in static timing analysis (STA), including 5 years of experience in a technical leadership capacity. Experience achieving full-chip timing convergence and authoring, reviewing, or validating timing constraints (e.g., Synopsys Design Constraints (SDC)). Experience using tool command language (Tcl) commands for timing analysis, timing closure, parasitic extraction, noise glitch, or crosstalk. Experience using electronic design automation (EDA) tools (e.g., PrimeTime, Tempus, Timevision, or STAR-RC). Experience analyzing cross-chip clock distribution networks. Learn more share Share Physical Design Lead, Static Timing Analysis link Copy link email Email a friend