Low Power Verification Engineer, Physical Design corporate_fare Google place Sunnyvale, CA, USA bar_chart Mid Mid Experience driving progress, solving problems, and mentoring more junior team members; deeper expertise and applied knowledge within relevant area. Google | Sunnyvale, CA, USA Minimum qualifications Bachelor's degree in Electrical Engineering, Computer Engineering, or equivalent practical experience. 8 years of experience performing post-layout physical netlist validation and low-power signoff within advanced ASIC design workflows. Experience with static low-power rule-checking tools (such as VCLP or CLP), including experience in debugging structural checks and signal corruption issues. Experience validating special low-power components (isolation cells, power switches, level shifters, retention registers, and always-on cells) across all stages from synthesis to place and route. Learn more share Share Low Power Verification Engineer, Physical Design link Copy link email Email a friend