Senior Design Verification Engineer, Silicon

Senior Design Verification Engineer, Silicon corporate_fare Google place Mountain View, CA, USA bar_chart Mid Mid Experience driving progress, solving problems, and mentoring more junior team members; deeper expertise and applied knowledge within relevant area. Google | Mountain View, CA, USA Minimum qualifications Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience. 8 years of experience verifying digital logic at RTL using SystemVerilog for ASICs or FPGAs. Experience verifying digital IP and subsystems. Experience working with design verification (DV) testbenches or environments. Learn more share Share Senior Design Verification Engineer, Silicon link Copy link email Email a friend