Senior Design Engineer, RTL

Senior Design Engineer, RTL corporate_fare Google place Mountain View, CA, USA bar_chart Mid Mid Experience driving progress, solving problems, and mentoring more junior team members; deeper expertise and applied knowledge within relevant area. Google | Mountain View, CA, USA Minimum qualifications Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience. 8 years of experience with IP Development or Integration. Experience in ASIC development with Verilog or VHDL (Vhsic Hardware Description Language). Experience in ASIC development with Verilog or VHDL (Vhsic Hardware Description Language). Learn more share Share Senior Design Engineer, RTL link Copy link email Email a friend