Senior TPU RTL Design Engineer, Networking, Inter-Chip Interconnects corporate_fare Google place Sunnyvale, CA, USA bar_chart Mid Mid Experience driving progress, solving problems, and mentoring more junior team members; deeper expertise and applied knowledge within relevant area. Google | Sunnyvale, CA, USA Minimum qualifications Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience. 5 years of experience in high-performance ASIC design. Experience architecting or designing RTL solutions for digital systems. Experience with high-speed interconnects. Experience developing networking IP across one or more layers, such as the media access control (MAC), link (L2), or physical (PHY) layers. Learn more share Share Senior TPU RTL Design Engineer, Networking, Inter-Chip Interconnects link Copy link email Email a friend