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Micron10K+ employees

New College Grad - Mixed Signal Design Engineer, HBM

Richardson, TXSalary not listedPosted yesterday

Immigration summary

Visa sponsorship

LikelyHigh confidence

This employer has recently sponsored work like this.

551 recent H-1B filings · 2 similar-role filings

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Green card sponsorship

Strong historyHigh confidence

This employer has recently sponsored green cards at scale.

57 recent certified PERM filings · 1 similar-role filing

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Job description

Our vision is to transform how the world uses information to enrich life for all.

Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever.

The Memory Systems Engineering team develops the digital and mixed-signal foundation that enables Micron's High Bandwidth Memory (HBM) products. The team works across architecture, PHY, design verification, DFT, and silicon validation functions to deliver innovative memory solutions that achieve demanding performance, power, and reliability targets.In this role, you'll receive mentorship from expert engineers while building expertise in sophisticated memory technologies. You will also contribute to the definition, implementation, integration, and validation of HBM base-die digital subsystems. You will collaborate with cross-disciplinary engineering groups to develop robust RTL solutions, support verification activities, and help ensure successful first-pass silicon execution. This position provides an opportunity to gain broad exposure to memory system design, silicon development methodologies, and AI-enabled engineering workflows.

Responsibilities

  • Define and implement digital micro-architecture for HBM base-die subsystems, including channel support logic, boot and initialization sequencing, training orchestration, configuration and status registers, telemetry, performance monitoring, and reliability features.
  • Translate system requirements into timing, power, and area objectives while partnering with physical layer and system architects; develop and maintain interface specifications for bus protocols, clock-domain crossings, and reset architectures.
  • Develop, integrate, and debug synthesizable SystemVerilog RTL, including multi-channel logic, interrupt handling, register maps, scan infrastructure, and design-for-test interfaces while supporting integration and ECO activities.
  • Work alongside design verification teams to build verification strategies, reach coverage goals, perform CDC/RDC analysis, and resolve RTL, testbench, and gate-level issues.
  • Support silicon bring-up and post-silicon validation through debug enablement, root-cause analysis, and partnership with DFT and test engineering teams; leverage AI-Assisted and AI-Enabled tools to improve engineering productivity, debug efficiency, and data-driven analysis.

Minimum Qualifications

  • Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or a related field.
  • Experience with digital design, SoC integration, or semiconductor development through academic projects, internships, research, or industry experience.
  • Solid understanding of SystemVerilog RTL development, clock and reset architectures, CDC/RDC methodologies, and low-power design concepts.
  • Understanding of design-for-debug and design-for-test principles and the ability to collaborate effectively within multi-functional engineering teams.
  • Experience working in AI-Assisted or AI-Enabled environments, or demonstrated willingness to apply AI tools to support engineering workflows, debug activities, and technical analysis.

Preferred Qualifications

  • Exposure to post-silicon validation, silicon bring-up, or structured hardware debug methodologies.
  • Familiarity with scan, MBIST, LBIST, or related test and debug architectures.
  • Experience contributing to verification planning and partnering with design verification teams to achieve functional and code coverage objectives.
  • Knowledge of micro-architecture optimization, timing closure concepts, and design tradeoffs related to constraints and path intent.
  • Experience Applying AI, Employing AI, or Using AI for data analysis, debug automation, productivity enhancement, or performance optimization within semiconductor design environments.

As a world leader in the semiconductor industry, Micron is dedicated to your personal wellbeing and professional growth. Micron benefits are designed to help you stay well, provide peace of mind and help you prepare for the future.  We offer a choice of medical, dental and vision plans in all locations enabling team members to select the plans that best meet their family healthcare needs and budget.  Micron also provides benefit programs that help protect your income if you are unable to work due to illness or injury, and paid family leave.  Additionally, Micron benefits include a robust paid time-off program and paid holidays.  For additional information regarding the Benefit programs available, please see the Benefits Guide posted on micron.com/careers/benefits.

Micron is proud to be an equal opportunity workplace and is an affirmative action employer. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, age, national origin, citizenship status, disability, protected veteran status, gender identity or any other factor protected by applicable federal, state, or local laws.

To learn about your right to work click here.

To learn more about Micron, please visit micron.com/careers

For US Sites Only: To request assistance with the application process and/or for reasonable accommodations, please contact Micron’s People Organization at  hrsupport_na@micron.com or 1-800-336-8918 (select option #3)

Micron Prohibits the use of child labor and complies with all applicable laws, rules, regulations, and other international and industry labor standards.

Micron does not charge candidates any recruitment fees or unlawfully collect any other payment from candidates as consideration for their employment with Micron.

AI alert: Candidates are encouraged to use AI tools to enhance their resume and/or application materials. However, all information provided must be accurate and reflect the candidate's true skills and experiences. Misuse of AI to fabricate or misrepresent qualifications will result in immediate disqualification.

Fraud alert: Micron advises job seekers to be cautious of unsolicited job offers and to verify the authenticity of any communication claiming to be from Micron by checking the official Micron careers website in the About Micron Technology, Inc.

Sponsorship evidence

Why Openbound reached the conclusions above.

Visa sponsorship evidence

Current posting

Silent on sponsorship

Employer H-1B history

551
recent certified H-1B filings
312
new-hire petitions
2
filings for similar roles
536
so far in FY2026

Filed titles like this role: hbm design engineer · design engineer - hbm design

More evidence details
  • 2 certified H-1B filings for this same role
  • 551 recent certified H-1B filings across the employer
  • Still filing this year — 536 filings in FY2026
  • 268 USCIS H-1B new-employment approvals, counted separately from LCA filings
  • Strong filing activity in TX
  • 611 further USCIS approvals for extensions or transfers
  • The posting says nothing about sponsorship either way

Strong filing activity in TX.

Green card sponsorship evidence

Employer PERM history

57
recent certified PERM filings
1
filings for similar roles
4
filings in this location
Certified PERM filings by fiscal year
202384
202428
202564
2026150YTD

Filing history reflects past employer behavior; it isn't a promise for this opening.

All open roles at Micron
How Openbound evaluates sponsorship

Visa history uses official U.S. Department of Labor H-1B LCA disclosure data and USCIS H-1B petition history. Green card history uses DOL PERM disclosure data. Each is read for the employer as a whole, for roles like this one, and for this location, weighted toward the most recent fiscal years.

An employer is matched to its filing entities by verified legal name and reviewed aliases; a match is never made on a name resemblance alone. Where no verified entity can be matched, the page says so and draws no conclusion from the absence. 780 filing titles were examined for this employer.

What this posting states outranks history in both directions, and an employer's published policy outranks past filings. Filing history reflects past behavior; it is not a promise of sponsorship for this opening, and none of this is legal advice.