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ON Semiconductor10K+ employees

Analog Design Engg - II

INSalary not listedPosted 2 days ago

Immigration summary

Visa sponsorship

LikelyMedium confidence

This employer has recently sponsored work like this.

112 recent H-1B filings

View visa evidence

Green card sponsorship

Some historyMedium confidence

This employer has recently sponsored green cards.

10 recent certified PERM filings · 1 similar-role filing

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Job description

OnSemi is seeking a Analog design Engineer, level II, NEW PRODUCT DEVELOPMENT, Power Management, to join our growing team in Bengaluru, India. This group is responsible for development of Power management products including LED drivers, SiC/MOS/IGBT/motor/GAN drivers, Switches and efuses for consumer, industrial and automotive applications. In this role, you will focus on the following

  • Design and develop an analog IP block from definition to IP delivery
  • Design and simulation at the block/IP level during execution phase, present the block results to review team in timely manner.
  • Work with and provide guidance to layout engg and monitors the progress of IP block layout
  • Work with validation, product engineering and test engineering teams to enable them to measure Si performance
  • Own technical outcomes of design, verification, implementation, and execution of power management IPs with complexities that can span from simple regulators to complex mixed-signal designs and control loops 
  • Able to plan and execute the work in timely manner aligning with full chip schedule. 

#L1-LK1

Responsibilities

OnSemi is seeking a Analog design Engineer, level II, NEW PRODUCT DEVELOPMENT, Power Management, to join our growing team in Bengaluru, India. This group is responsible for development of Power management products including LED drivers, SiC/MOS/IGBT/motor/GAN drivers, Switches and efuses for consumer, industrial and automotive applications. In this role, you will focus on the following

  • Design and develop an analog IP block from definition to IP delivery
  • Design and simulation at the block/IP level during execution phase, present the block results to review team in timely manner.
  • Work with and provide guidance to layout engg and monitors the progress of IP block layout
  • Work with validation, product engineering and test engineering teams to enable them to measure Si performance
  • Own technical outcomes of design, verification, implementation, and execution of power management IPs with complexities that can span from simple regulators to complex mixed-signal designs and control loops 
  • Able to plan and execute the work in timely manner aligning with full chip schedule. 

#L1-LK1

Qualifications

BS in Electrical Engineering or related + 4 years of experience, or MS + 2 years of experience

Qualification

  • Solid track record of delivering block/IP level design 
  • Understand and execute IP design, simulations methods, boundary conditions, stress and reliability simulations, PVT/PMC/SOA simulations.
  • Good communication skills to make detailed technical presentations  
  • Good understanding of various building blocks like LDOs, gate drivers, comparators, linear regulators, gm-stages, charge pumps etc 
  • Experience in SiC/GAN/LED/Motor, Efuse and smart Switches etc is plus
  • Strong Analog IC design skills, debug of complex silicon problems using simulations and/or bench testing 
  • Understanding of power transistor Design, Layout, and Robustness 
  • Experience in system tools such as Simplis or MATLAB for architectural simulations, Cadence Spectre for schematic capture, simulation 
  • Strong verbal and written communication skills 
  • Ability to quickly ramp on new systems and processes 
  • Demonstrated strong interpersonal, analytical and problem-solving skills 
  • Ability to work in teams 

#L1-LK1

onsemi

(Nasdaq: ON) is driving disruptive innovations to help build a better future. With a focus on automotive and industrial end-markets, the company is accelerating change in megatrends such as vehicle electrification and safety, sustainable energy grids, industrial automation, and 5G and cloud infrastructure. With a highly differentiated and innovative product portfolio, onsemi creates intelligent power and sensing technologies that solve the world’s most complex challenges and leads the way in creating a safer, cleaner, and smarter world.

More details about our company benefits can be found here:

https://www.onsemi.com/careers/career-benefits

Sponsorship evidence

Why Openbound reached the conclusions above.

Visa sponsorship evidence

Current posting

Silent on sponsorship

Other openings

7 of 697 recent openings at this employer state a sponsorship restriction.

Employer H-1B history

112
recent certified H-1B filings
76
new-hire petitions
0
filings for similar roles
96
so far in FY2026

Filed titles like this role: analog engineer · firmware engineer · member of technical analog design engineer · analog design engineer

More evidence details
  • 5 certified H-1B filings for closely related roles, though none for this exact title
  • 112 recent certified H-1B filings across the employer
  • Still filing this year — 96 filings in FY2026
  • 13 USCIS H-1B new-employment approvals, counted separately from LCA filings
  • 78 further USCIS approvals for extensions or transfers
  • 7 other recent postings at this company state a sponsorship restriction
  • The supporting filings are for related work, not for this exact role
  • The posting says nothing about sponsorship either way
  • No filing activity is recorded for this job's location

Green card sponsorship evidence

Employer PERM history

10
recent certified PERM filings
1
filings for similar roles
Certified PERM filings by fiscal year
20238
20244
202515
202624YTD

Filing history reflects past employer behavior; it isn't a promise for this opening.

All open roles at ON Semiconductor
How Openbound evaluates sponsorship

Visa history uses official U.S. Department of Labor H-1B LCA disclosure data and USCIS H-1B petition history. Green card history uses DOL PERM disclosure data. Each is read for the employer as a whole, for roles like this one, and for this location, weighted toward the most recent fiscal years.

An employer is matched to its filing entities by verified legal name and reviewed aliases; a match is never made on a name resemblance alone. Where no verified entity can be matched, the page says so and draws no conclusion from the absence. 194 filing titles were examined for this employer.

What this posting states outranks history in both directions, and an employer's published policy outranks past filings. Filing history reflects past behavior; it is not a promise of sponsorship for this opening, and none of this is legal advice.